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generalplus technology inc. reserves the right to change this documentation without prior notice. information provided by gene ralplus technology inc. is believed to be accurate and reliable. however, generalplus technology inc. makes no warranty for any errors which may appear in this document. contact generalplus technology inc. to obtain the latest version of devi ce specifications before plac ing your order. no responsibility is assumed by generalplus technology inc. for any infringement of patent or other rights of third parties which may result from its use. in addition, generalplus products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the expre ss written approval of generalplus. nov 02, 2012 version 1.0 g g p p r r 2 2 5 5 l l 0 0 8 8 0 0 5 5 e e 8m-bit [x 1/x 2/x 4] cmos serial flash
gpr25l0805e ? generalplus technology inc. proprietary & confidential 2 nov 02, 2012 version: 1.0 table of contents page 1. features....................................................................................................................... ........................................................................... 4 1.1. g eneral ............................................................................................................................... ............................................................... 4 1.2. p erformance ............................................................................................................................... ....................................................... 4 1.3. s oftware f eatures ............................................................................................................................... ............................................ 4 1.4. h ardware f eatures ............................................................................................................................... ........................................... 4 2. general description .................................................................................................................... ...................................................... 5 3. pin configurations ................................................................................................................. ............................................................ 5 3.1. 8-pin sop (200 mil ) .............................................................................................................................. ............................................... 5 4. pin description.................................................................................................................... .................................................................. 5 5. block diagram ........................................................................................................................ .............................................................. 6 6. data protection..................................................................................................................... .............................................................. 7 6.1. m emory o rganization ............................................................................................................................... ......................................... 8 7. device operation...................................................................................................................... .......................................................... 10 8. command description .................................................................................................................... .................................................. 11 8.1. w rite e nable (wren)......................................................................................................................... ............................................. 12 8.2. w rite d isable (wrdi) ......................................................................................................................... ............................................. 12 8.3. r ead i dentification (rdid) ......................................................................................................................... ..................................... 12 8.4. r ead s tatus r egister (rdsr) ......................................................................................................................... ............................... 12 8.5. w rite s tatus r egister (wrsr) ......................................................................................................................... ............................. 13 8.6. r ead d ata b ytes (read)......................................................................................................................... ......................................... 14 8.7. r ead d ata b ytes at h igher s peed (fast_read).................................................................................................................... ....... 14 8.8. 2 x i/o r ead m ode (2read)........................................................................................................................ ...................................... 14 8.9. 4 x i/o r ead m ode (4read)........................................................................................................................ ...................................... 14 8.10. s ector e rase (se) ........................................................................................................................... ................................................ 15 8.11. b lock e rase (be) ........................................................................................................................... .................................................. 15 8.12. c hip e rase (ce) ........................................................................................................................... ..................................................... 15 8.13. p age p rogram (pp) ........................................................................................................................... ............................................... 15 8.14. 4 x i/o p age p rogram (4pp) .......................................................................................................................... ................................... 16 8.15. d eep p ower - down (dp) ........................................................................................................................... ........................................ 16 8.16. r elease from d eep p ower - down (rdp), r ead e lectronic s ignature (res) ............................................................................. 16 8.17. r ead e lectronic m anufacturer id & d evice id (rems), (rems2), (rems4) ............................................................................. 16 8.18. e nter s ecured otp (enso) ......................................................................................................................... .................................. 17 8.19. e xit s ecured otp (exso) ......................................................................................................................... ...................................... 17 8.20. r ead s ecurity r egister (rdscur) ....................................................................................................................... ........................ 17 8.21. w rite s ecurity r egister (wrscur) ....................................................................................................................... ...................... 17 9. power-on state .......................................................................................................................... ........................................................ 19 10. electrical specifications ................................................................................................................. ............................................ 20 10.1. a bsolute m aximum r atings ............................................................................................................................... .............................. 20 10.2. c apacitance ta = 25 , f = 1.0 mh z ............................................................................................................................... ................. 20 10.3. dc c haracteristics (t emperature = -40 c to 85 c for i ndustrial grade , vcc = 2.7v ~ 3.6v)(t able 9) ................................ 22 10.4. ac c haracteristics (t emperature = -40 c to 85 c for i ndustrial grade , vcc = 2.7v ~ 3.6v)(t able 10) .............................. 23
gpr25l0805e ? generalplus technology inc. proprietary & confidential 3 nov 02, 2012 version: 1.0 10.5. t iming a nalysis ............................................................................................................................... .................................................. 24 10.6. i nitial d elivery s tate ............................................................................................................................... ........................................ 34 11. recommended operating conditions..................................................................................................................... .................... 35 11.1. a t d evice p ower -u p ............................................................................................................................... ......................................... 35 12. erase and programming performance .................................................................................................................... ................ 36 13. data retention ...................................................................................................................... ............................................................. 36 14. latch-up characteristics ................................................................................................................ ............................................. 37 15. ordering information .................................................................................................................... ................................................. 38 16. package information.................................................................................................................... ................................................... 39 16.1. t itle : p ackage o utline for sop 8l (200mil) ....................................................................................................................... .......... 39 16.2. d imensions (i nch dimensions are derived from the original mm dimensions ).............................................................................. 39 17. disclaimer..................................................................................................................... ........................................................................ 40 18. revision history ........................................................................................................................ ......................................................... 41
gpr25l0805e ? generalplus technology inc. proprietary & confidential 4 nov 02, 2012 version: 1.0 8m-bit [x 1/x 2/x 4] cmos serial flash 1. features 1.1. general ? serial peripheral interface compatible -- mode 0 and mode 3 ? 8m: 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two i/o read mode) structure or 2,097,152 x 4 bits (four i/o read mode) structure ? 256 equal sectors with 4k byte each - any sector can be erased individually ? 16 equal blocks with 64k byte each - any block can be erased individually ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to vcc +1v 1.2. performance ? high performance - fast read - 1 i/o: 108mhz with 8 dummy cycles - 2 i/o: 80mhz (2.7v~3.6v); 104mhz (3.0v~3.6v) with 4 dummy cycles - 4 i/o: 108mhz with 6 dummy cycles - fast access time: 108mhz serial clock - serial clock of two i/o read mode: 80mhz (2.7v~3.6v); 104mhz (3.0v~3.6v) - serial clock of four i/o read mode: 108mhz, which is equivalent to 432mhz - fast program time: 0.7ms(typ.) and 3ms(max.)/page (256-byte per page) - byte program time: 9us (typical) - fast erase time: 60ms (typ.)/sector (4k-byte per sector) ; 0.4s(typ.) /block (64k-byte per block); 3s(typ.) /chip ? low power consumption - low active read current: 25ma(max.) at 108mhz, and 10ma(max.) at 50mhz - low active programming current: 20ma (max.) - low active erase current: 20ma (max.) - low standby current: 20ua (typ.) ; 50ua (max.) - deep power-down current: 3ua (typ.) ; 20ua (max.) ? minimum 100,000 erase/program cycles ? 20 years data retention 1.3. software features ? input data format - 1-byte command code ? advanced security features - block lock protection the bp0-bp3 status bit defines the size of the area to be software protection against progr am and erase instructions - additional 4k-bit secured otp for unique identifier ? auto erase and auto program algorithm - automatically erases and verifies data at selected sector - automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state first) ? status register feature ? electronic identification - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - all rems, rems2 and rems4 commands for 1-byte manufacturer id and 1-byte device id 1.4. hardware features ? sclk input - serial clock input ? si/sio0 - serial data input or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? so/sio1 - serial data output or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? wp#/sio2 - hardware write protection or serial data input/output for 4 x i/o read mode ? nc/sio3 - nc pin or serial data input/output for 4 x i/o read mode ? package - 8-pin sop (200mil)
gpr25l0805e ? generalplus technology inc. proprietary & confidential 5 nov 02, 2012 version: 1.0 2. general description the gpr25l0805e is 8,388,608 bit se rial flash memory, which is configured as 1,048,576 x 8 internally. when it is in two or four i/o read mode, the structure becomes 4,194,304 bits x 2 or 2,097,152 bits x 4. the gpr25l0805e feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. when it is in two i/o read mode, the si pin and so pin become sio0 pin and sio1 pin for address/dummy bits input and data output. when it is in four i/o read mode, the si pin, so pin, wp# pin and nc pin become sio0 pin, sio1 pin, sio2 pin, and sio3 pin for address/dummy bits input and data output. the gpr25l0805e provides sequential read operation on whole chip. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. program command is executed on byte basis, or page (256 bytes) basis, and erase command is executes on sector (4k-byte), or block (64k-byte), or whole chip basis. to provide user with ease of interf ace, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. secured otp and block protection, please see security feature and write status register section for more details. when the device is not in operation and cs# is high, it is put in standby mode and draws less than 100ua dc current. the gpr25l0805e utilizes proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. additional feature comparison protection and security read performance identifier additional features part name flexible block protection (bp0-bp3) 4k-bit secured otp 2 i/o read 4 i/o read res (command: ab hex) rems (command: 90 hex) rems2 (command: ef hex) rems4 (command: df hex) rdid (command: 9f hex) gpr25l0805e v v v v 13 (hex) c2 13 (hex) (if add=0) c2 13 (hex) (if add=0) c2 13 (hex) (if add=0) c2 20 14 (hex) 3. pin configurations 3.1. 8-pin sop (200mil) 4. pin description symbol description cs# chip select si/sio0 serial data input (for 1 x i/o) / serial data input & output (for 2xi/o or 4xi/o read mode) so/sio1 serial data output (for 1 x i/o) serial data input & output (for 2xi/o or 4xi/o read mode) sclk clock input wp#/sio2 write protection: connect to gnd or serial data input & output (for 4xi/o read mode) nc/sio3 nc pin (not connect) or serial data input & output (for 4xi/o read mode) vcc + 3.3v power supply gnd ground
gpr25l0805e ? generalplus technology inc. proprietary & confidential 6 nov 02, 2012 version: 1.0 5. block diagram
gpr25l0805e ? generalplus technology inc. proprietary & confidential 7 nov 02, 2012 version: 1.0 6. data protection during power transition, there may be some false system level signals which result in inadvertent erasure or programming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that th e memory contents can only be changed after specific comm and sequences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power-up and power-down or from system noise. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - write disable (wrdi) command completion - write status register (wrsr) command completion - page program (pp) command completion - page program (4pp) command completion - sector erase (se) command completion - block erase (be) command completion - chip erase (ce) command completion ? deep power down mode: by entering deep power down mode, the flash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic signature command (res). ? advanced security features: there are some protection and security features which protect content from inadvertent write and hostile access. i. block lock protection - the software protected mode (spm) use (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the protected area definition is show n as table of "protected area sizes", the protected areas are mo re flexible which may protect various area by setting value of bp0-bp3 bits. please refer to table of "protected area sizes". - the hardware protected mode (hpm) use wp#/sio2 to protect the (bp3, bp2, bp1, bp0) bits and srwd bit. if the qe bit is set, the feature of hpm will be disabled. table2. protected area sizes status bit protect level bp3 bp2 bp1 bp0 8mb 0 0 0 0 0 (none) 0 0 0 1 1 (1block, 1/16 area, block#15) 0 0 1 0 2 (2blocks, 1/8 area, block#14-15) 0 0 1 1 3 (4blocks, 1/4 area, block#12-15) 0 1 0 0 4 (8blocks, 1/2 area, block#8-15) 0 1 0 1 5 (16blocks, all) 0 1 1 0 6 (16blocks, all) 0 1 1 1 7 (16blocks, all) 1 0 0 0 8 (16blocks, all) 1 0 0 1 9 (16blocks, all) 1 0 1 0 10 (16blocks, all) 1 0 1 1 11 (8blocks, 1/2 area, block#0-7) 1 1 0 0 12 (12blocks, 3/4 area, block#0-11) 1 1 0 1 13 (14blocks, 7/8 area, block#0-13) 1 1 1 0 14 (15block, 15/16 area, block#0-14) 1 1 1 1 15 (16blocks, all) ii. additional 4k-bit secured otp for unique identifier: to provide 4k-bit one-time prog ram area for setting device unique serial number - which may be set by factory or system maker. please refer to table 3. 4k-bit secured otp definition. - security register bit 0 indicates whether the chip is locked by factory or not. - to program the 4k-bit secured otp by entering 4k-bit secured otp mode (with enso command), and going through normal program procedure, and then exiting 4k-bit secured otp mode by writing exso command. - customer may lock-down the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to table of "security register definition" for security register bit definition and table of "4k-bit secured otp definition" for address range definition. - note: once lock-down whatever by factory or customer, it cannot be changed any more. while in 4k-bit secured otp mode, array access is not allowed.
gpr25l0805e ? generalplus technology inc. proprietary & confidential 8 nov 02, 2012 version: 1.0 table 3. 4k-bit secured otp definition address range size standard factory lock customer lock xxx000~xxx00f 128-bit esn (electrical serial number) xxx010~xxxfff 3968-bit n/a determined by customer 6.1. memory organization memory organization (8mb) block sector address range 255 0ff000h 0fffffh : : : 15 240 0f0000h 0f0fffh 239 0ef000h 0effffh : : : 14 224 0e0000h 0e0fffh 223 0df000h 0dffffh : : : 13 208 0d0000h 0d0fffh 207 0cf000h 0cffffh : : : 12 192 0c0000h 0c0fffh 191 0bf000h 0bffffh : : : 11 176 0b0000h 0b0fffh 175 0af000h 0affffh : : : 10 160 0a0000h 0a0fffh 159 09f000h 09ffffh : : : 9 144 090000h 090fffh 143 08f000h 08ffffh : : : 8 128 080000h 080fffh 127 07f000h 07ffffh : : : 7 112 070000h 070fffh 111 06f000h 06ffffh : : : 6 96 060000h 060fffh 95 05f000h 05ffffh : : : 5 80 050000h 050fffh 79 04f000h 04ffffh : : : 4 64 040000h 040fffh 63 03f000h 03ffffh 3 : : :
gpr25l0805e ? generalplus technology inc. proprietary & confidential 9 nov 02, 2012 version: 1.0 block sector address range 48 030000h 030fffh 47 02f000h 02ffffh : : : 2 32 020000h 020fffh 31 01f000h 01ffffh : : : 1 16 010000h 010fffh 15 00f000h 00ffffh : : : 2 002000h 002fffh 1 001000h 001fffh 0 0 000000h 000fffh
gpr25l0805e ? generalplus technology inc. proprietary & confidential 10 nov 02, 2012 version: 1.0 7. device operation 1. before a command is issued, st atus register should be checked to ensure device is ready for the intended operation. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, so pin of this lsi should be high-z. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock (sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as figure 1. 5. for the following instructions: rdid, rdsr, rdscur, read, fast_read, 2read, 4read,res, rems, rems2 and rems4 the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be, ce, pp, 4pp, cp, rdp, dp, enso, exso, and wrscur, the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of write status register, program, erase operation, to access the memory array is neglected and not affect the current operation of write status register, program, erase. figure1. spi modes supported note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cp ha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported.
gpr25l0805e ? generalplus technology inc. proprietary & confidential 11 nov 02, 2012 version: 1.0 8. command description table 5. command set command (byte) wren (write enable) wrdi (write disable) rdid (read identification) rdsr (read status register) wrsr (write status register) read (read data) fast read (fast read data) 2read (2 x i/o read command) note1 4read (4 x i/o read command) 1st byte 06 (hex) 04 (hex) 9f (hex) 05 (hex) 01 (hex) 03 (hex) 0b (hex) bb (hex) eb (hex) 2nd byte values ad1 (a23-a16) ad1 add(2) add(4) & dummy (4) 3rd byte ad2 (a15-a8) ad2 add(2) & dummy (2) dummy (4) 4th byte ad3 (a7-a0) ad3 5th byte dummy action sets the (wel) write enable latch bit resets the (wel) write enable latch bit outputs jedec id: 1-byte manufacturer id & 2-byte device id to read out the values of the status register to write new values to the status register n bytes read out until cs# goes high n bytes read out until cs# goes high n bytes read out by 2xi/o until cs# goes high n bytes read out by 4 x i/o until cs# goes high command (byte) 4pp (quad page program) se (sector erase) be (block erase) ce (chip erase) pp (page program) dp (deep power down) rdp (release from deep power down) res (read electronic id) 1st byte 38 (hex) 20 (hex) d8 (hex) 60 or c7 (hex) 02 (hex) b9 (hex) ab (hex) ab (hex) 2nd byte ad1 ad1 ad1 ad1 x 3rd byte ad2 ad2 ad2 x 4th byte ad3 ad3 ad3 x action quad input to program the selected page to erase the selected sector to erase the selected block to erase whole chip to program the selected page enters deep power down mode release from deep power down mode to read out 1-byte device id command (byte) rems (read electronic manufacturer & device id) rems2 (read id for 2x i/o mode) rems4 (read id for 4x i/o mode) enso (enter secured otp) exso (exit secured otp) rdscur (read security register) wrscur (write security register) release read enhanced 1st byte 90 (hex) ef (hex) df (hex) b1 (hex) c1 (hex) 2b (hex) 2f (hex) ffh (hex) 2nd byte x x x x 3rd byte x x x x 4th byte add (note 2) add (note 2) add (note 2) x action output the manufacturer id & device id output the manufacturer id & device id output the manufacturer id & device id to enter the 4k-bit secured otp mode to exit the 4k-bit secured otp mode to read value of security register to set the lock-down bit as "1" (once lock-down, cannot be updated) all these commands ffh,00h,aah or 55h will escape the performance enhance mode note 1: the count base is 4-bit for add(2) and dummy(2) because of 2 x i/o. and the msb is on si/sio1 which is different from 1 x i/o condition. note 2: add=00h will output the manufacturer id firs t and add=01h will output device id first. note 3: it is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mod e.
gpr25l0805e ? generalplus technology inc. proprietary & confidential 12 nov 02, 2012 version: 1.0 8.1. write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, 4pp, cp, se, be, ce, and wrsr, which are intended to change the device content, should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes low sending wren instruction code cs# goes high. (please refer to figure 9) 8.2. write disable (wrdi) the write disable (wrdi) instruct ion is for resetting write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes low sending wrdi instruction code cs# goes high. (please refer to figure 10) the wel bit is reset by following situations: - power-up - write disable (wrdi) instruction completion - write status register (wrsr) instruction completion - page program (pp) instruction completion - quad page program (4pp) instruction completion - sector erase (se) instruction completion - block erase (be) instruction completion - chip erase (ce) instruction completion 8.3. read identification (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the manufacturer id is c2(hex), the memory type id is 20(hex) as the first-byte device id, and the individual device id of second- byte id are listed as table of "id definitions". (please refer to "table 7. id definitions") the sequence of issuing rdid instruction is: cs# goes low sending rdid instruction code 24-bits id data out on so to end rdid operation can use cs# to high at any time during data out. (please refer to figure 11) while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. 8.4. read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status regist er condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes low sending rdsr instruction code status register data out on so (please refer to figure 12) the definition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. if the program/erase command is applied to a protected memory area, the arra y data will not be affected and wel bit will be reset. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indica te the protected area (as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits define the protected area of the memory to against page program (pp), sector erase (se), block eras e (be) and chip erase (ce) instructions (only if all block protect bits set to 0, the ce instruction can be executed). qe bit. the quad enable (qe) bit, non-volatile bit, performs quad when it is reset to "0" (factory default) to enable wp# or is set to "1" to enable quad sio2 and sio3. once the system goes into quad i/o mode, the feature of hpm will be disable. srwd bit. the status register write disable (srwd) bit, non-volatile bit, which is set to "0" (factory default). the srwd bit is operated together with write protection (wp#/sio2) pin for providing hardware protection m ode. the hardware protection mode requires srwd sets to 1 and wp#/sio2 pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3, bp2, bp1, bp0) are read only.
gpr25l0805e ? generalplus technology inc. proprietary & confidential 13 nov 02, 2012 version: 1.0 status register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) qe (quad enable) bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 1=quad enable 0=not quad enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit non-volatile bi t non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bi t factory default=0 factory default=0 factory default=0 factory default=0 factory default=0 factory default=0 factory default=0 factory default=0 note 1: please refer to the "table 2. protected area sizes". 8.5. write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to define the protected area of memory (as shown in table 2). the wrsr also can set or reset the quad enable (qe) bit and set or reset the status register write disable (srwd) bit in accordance with write protection (wp#/sio2) pin signal, but has no effect on bit1(wel) and bit0 (wip) of the status register. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes low sending wrsr instruction code status register data on si cs# goes high. (please refer to figure 13) the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. table 6. protection modes mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp3 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp0-bp3 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase. note: 1. as defined by the values in the block protect (bp3, bp2, bp1 , bp0) bits of the status register, as shown in table 2. as the above table showing, the summary of the software pr otected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when srwd bit=0, no matter wp#/sio2 is low or high, the wren instruction may set the wel bit and can change the values of srw d, bp3, bp2, bp1, bp0. the protected area, which is defined by bp3, bp2, bp1, bp0, is at software protected mode (spm). - when srwd bit=1 and wp#/sio2 is high, the wren instruction may set the wel bit can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defined by bp3, bp2, bp1, bp0, is at software protected mode (spm). note: if srwd bit=1 but wp#/sio2 is low, it is impossible to write the status register even if the wel bit has previously been set. i t is rejected to write the status register and not be executed. hardware protected mode (hpm):
gpr25l0805e ? generalplus technology inc. proprietary & confidential 14 nov 02, 2012 version: 1.0 - when srwd bit=1, and then wp#/sio2 is low (or wp#/sio2 is lo w before srwd bit=1), it enters the hardware protected mode (hpm) . the data of the protected area is protected by software prot ected mode by bp3, bp2, bp1, bp0 and hardwar e protected mode by the wp#/sio2 to aga inst data modification. note: to exit the hardware protected mode requires wp#/sio2 driving high once the hardware protected mode is entered. if the wp#/sio2 pin is permanently connected to high, the hardware protected mode can never be entered ; only can use software protected mode via bp3, bp2, bp1, bp 0. if the qe bit is set, the feature of hpm will be disabled. 8.6. read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes low sending read instruction code 3-byte address on si data out on so to end read operation can use cs# to high at any time during data out. (please refer to figure 14) 8.7. read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. t he address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code 3- byte address on si 1-dummy byte (default) address on si data out on so to end fast_read operation can use cs# to high at any time during data out. (please refer to figure 15) while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any impact on the program/erase/write status register current cycle. 8.8. 2 x i/o read mode (2read) the 2read instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleav e on 2 i/o pins) shift out on the falling edge of sclk at a maximum frequency ft. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 2read instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing 2read instruction is: cs# goes low sending 2read instruction 24-bit address interleave on sio1 & sio0 4-bit dummy cycle on sio1 & sio0 data out interleave on sio1 & sio0 to end 2read operation can use cs# to high at any time during data out (please refer to figure 16). while program/erase/write status register cycle is in progress, 2read instruction is rejected without any impact on the program/erase/write status register current cycle. 8.9. 4 x i/o read mode (4read) the 4read instruction enable quad throughput of serial flash in read mode. a quad enable (qe) bit of status register must be set to "1" before sending the 4read instruction. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the first address byte can be at any location. the address is autom atically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4read instruction. the ad- dress counter rolls over to 0 when the highest address has been reached. once writing 4read instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing 4read instruction is: cs# goes low sending 4read instruction 24-bit address interleave on sio3, sio2, sio1 & sio0 6 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out (please refer to figure 17). another sequence of issuing 4 read instruction especially useful in random access is: cs# goes low sending 4 read instruction 3-bytes address interleave on sio3, sio2, sio1 & sio0 performance enhance toggling bit p[7:0] 4 dummy cycles data out still cs# goes high cs# goes low (reduce 4 read instruction) 24-bit random access address (please refer to figure 18 for 4x i/o read enhance performance mode timing waveform). in the performance-enhancing mode (note of figure 18), p[7:4] must be toggling with p[3:0] ; likewise p[7:0]=a5h,5ah,f0h or 0fh can make this mode continue and reduce the next 4read
gpr25l0805e ? generalplus technology inc. proprietary & confidential 15 nov 02, 2012 version: 1.0 instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh,00h,aah or 55h. and afterwards cs# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. while program/erase/write status register cycle is in progress, 4read instruction is rejected without any impact on the program/erase/write status register current cycle. 8.10. sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see table 4) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the eighth bit of last address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most significant address) select the sector address. the sequence of issuing se instruction is: cs# goes low sending se instruction code 3-byte address on si cs# goes high. (please refer to figure 19) the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the sector erase (se) instruction will not be executed on the page. 8.11. block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the inst ruction is used for 64k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (see table 3) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the eighth bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code 3-byte address on si cs# goes high. (please refer to figure 20) the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the block erase (be) instruction will not be executed on the page. 8.12. chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the chip erase (ce). the cs# must go high exactly at the byte boundary(the eighth bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes low sending ce instruction code cs# goes high. (please refer to figure 21) the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the chip er ase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected by bp3, bp2, bp1, bp0 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp2, bp1, bp0 all set to "0". 8.13. page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. if the entire 256 data bytes are going to be programmed, a7-a0 (the eight least significant address bits) should be set to 0. if the eight least significant address bits (a7-a0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address a7-a0 are all 0). if more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. if less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 3-byte address on si at least 1-byte on data on si cs# goes high. (please refer to figure 22) the cs# must be kept to low during the whole page program cycle; the cs# must go high exactly at the byte boundary (the eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit
gpr25l0805e ? generalplus technology inc. proprietary & confidential 16 nov 02, 2012 version: 1.0 still can be check out during the p age program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the page program (pp) instruction will not be executed. 8.14. 4 x i/o page program (4pp) the quad page program (4pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit and quad enable (qe) bit must be set to "1" before sending the quad page program (4pp). the quad page programming takes four pins: sio0, sio1, sio2, and sio3, which can raise programmer performance and the effectiveness of application of lower clock less than 33mhz. for system with faster clock, the quad page program cannot provide more actual favo rs, because the required internal page program time is far more than the time data flows in. therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 33mhz below. the other function descriptions are as same as standard page program. the sequence of issuing 4pp instruction is: cs# goes low sending 4pp instruction code 3-byte address on sio[3:0] at least 1-byte on data on sio[3:0] cs# goes high. (please refer to figure 23) 8.15. deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consum ption (to entering the deep power-down mode), the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not active and all write/program/erase instruction are ignored. when cs# goes high, it's only in standby mode not deep power-down mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes low sending dp instruction code cs# goes high. (please refer to figure 24) once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction. (those instructions allow the id being reading out). when power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode and reducing the current to isb2. 8.16. release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specified in "table 10. ac characteristics". once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. the rdp instruction is only for releasing from deep power down mode. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id definitions. this is not the same as rdid instruction. it is not recommended to use for new design. fo r new design, please use rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. the sequence is shown as figure 25, figure 26. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeatedly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. 8.17. read electronic manufacturer id & device id (rems), (rems2), (rems4) the rems, rems2 & rems4 instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the rems4 instruction is recommended to use for 4 i/o identification. the rems, rems2 & rems4 instruction is very similar to the release from power-down/device id instruction. the instruction is initiated by driving the cs# pin low and shift the instruction code "90h" or "efh" or "dfh" followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id for
gpr25l0805e ? generalplus technology inc. proprietary & confidential 17 nov 02, 2012 version: 1.0 (c2h) and the device id are shifted out on the falling edge of sclk with most significant bit (m sb) first as shown in figure 27. the device id values are listed in table of id definitions. if the one-byte address is initially set to 01h, then the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. table 7. id definitions manufacturer id memory type memory density rdid command c2 20 14 electronic id res command 13 manufacturer id device id rems/rems2/rems4/ command c2 13 8.18. enter secured otp (enso) the enso instruction is for entering the additional 4k-bit secured otp mode. the additional 4k-bit secured otp is independent from main array, which may use to store unique serial number for system identifier. after entering the secured otp mode, and then follow standard read or program, procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes low sending enso instruction to enter secured otp mode cs# goes high. please note that wrsr/wrscur commands are not acceptable during the access of secure otp region, once security otp is lock down, only read related commands are valid. 8.19. exit secured otp (exso) the exso instruction is for exiting the additional 4k-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes low sending exso instruction to exit secured otp mode cs# goes high. 8.20. read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is: cs# goes low sending rdscur instruction security register data out on so cs# goes high. the definition of the security register bits is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory before ex-factory or not. when it is "0", it indicates non- factory lock; "1" indicates factory- lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for customer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 4k-bit secured otp area cannot be update any more. while it is in 4k-bit secured otp mode, array access is not allowed. table 8. security register definition bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 x x x x x x ldso (indicate if lo ck-down secured otp indicator bit reserved reserved reserved reserved reserved reserved 0 = not lock-down 1 = lock-down (cannot program/erase otp) 0 = non-factory lock 1 = factory lock volatile bit volatile bit volatile bi t volatile bit volatile bit volatile bit non-volatile bit non-volatile bit 8.21. write security register (wrscur) the wrscur instruction is for changing the values of security register bits. unlike write status register, the wren instruction is not required before sending wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 4k-bit secured otp area. once the ldso bit is set to "1", the secured otp area cannot
gpr25l0805e ? generalplus technology inc. proprietary & confidential 18 nov 02, 2012 version: 1.0 be updated any more. the sequence of issuing wrscur instruction is: cs# goes low sending wrscur instruction cs# goes high. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
gpr25l0805e ? generalplus technology inc. proprietary & confidential 19 nov 02, 2012 version: 1.0 9. power-on state the device is at below states when power-up: - standby mode (please note it is not deep power-down mode) - write enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power-up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por ) circuit may protect the device from data corruption and inadvertent data change during power up state. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the write, erase, and program command should be sent after the below time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. please refer to the figure of "power-up timing". note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uf)
gpr25l0805e ? generalplus technology inc. proprietary & confidential 20 nov 02, 2012 version: 1.0 10. electrical specifications 10.1. absolute maximum ratings rating value ambient operating temperature industrial grade -40c to 85c storage temperature -55c to 125c applied input voltage -0.5v to 4.6v applied output voltage -0.5v to 4.6v vcc to ground potential -0.5v to 4.6v notice: 1. stresses greater than those listed under absolute maximum rati ngs may cause permanent damage to the device. this is stress r ating only and functional operational sections of this s pecification is not implied. exposure to ab solute maximum rating conditions for extend ed period may affect reliability. 2. specifications contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot vss to -2.0v and vcc to +2.0v for periods up to 20ns, see figure 2, 3 figure2.maximum negative overshoot waveform figure3. maximum positive overshoot waveform 10.2. capacitance ta = 25 , f = 1.0 mhz symbol parameter min. typ. max. unit conditions cin input capacitance - - 6 pf vin = 0v cout output capacitance - - 8 pf vout = 0v figure4. input test waveforms and measurement level
gpr25l0805e ? generalplus technology inc. proprietary & confidential 21 nov 02, 2012 version: 1.0 figure5. output loading
gpr25l0805e ? generalplus technology inc. proprietary & confidential 22 nov 02, 2012 version: 1.0 10.3. dc characteristics (temperature = -40 c to 85 c for industrial grade, vcc = 2.7v ~ 3.6v)(table9) symbol parameter notes min. typ. max. units test conditions ili input load current 1 - - 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 - - 2 ua vcc = vcc max, vout = vcc or gnd isb1 vcc standby current 1 - 20 50 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current - - 3 20 ua vin = vcc or gnd, cs# = vcc 25 ma f=108mhz, ft=104mhz(vcc=3.0v~3.6v, 2 x i/o read) fq=108mhz (4 x i/o read) sclk=0.1vcc/0.9vcc, so=open 15 ma ft=80mhz (2 x i/o read) sclk=0.1vcc/0.9vcc, so=open icc1 vcc read 1 - - 10 ma f=50mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 - - 20 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current - - - 20 ma program status register in progress, cs#=vcc icc4 vcc sector erase current (se) 1 - - 20 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 - - 20 ma erase in progress, cs#=vcc vil input low voltage - -0.5 - 0.3vcc v vih input high voltage - 0.7vcc - vcc+0.4 v vol output low voltage - - - 0.4 v iol = 1.6ma voh output high voltage - vcc-0.2 - - v ioh = -100ua notes: 1. typical values at vcc = 3.3v, t = 25c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation. 3. it is measured under checkboard pattern.
gpr25l0805e ? generalplus technology inc. proprietary & confidential 23 nov 02, 2012 version: 1.0 10.4. ac characteristics (temperature = -40 c to 85 c for industrial grade, vcc = 2.7v ~ 3.6v)(table10) symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, pp, se, be, ce, dp, res, rdp, wren, wrdi, rdid, rdsr, wrsr d.c. - 108 mhz frsclk fr clock frequency for read instructions - - 50 mhz 2.7v-3.6v - - 80 mhz ft clock frequency f o r 2read instructions 3.0v-3.6v - - 104 mhz ftsclk fq clock frequency for 4read instructions - - 108 mhz f4pp clock frequency for 4pp (quad page program) - - 33 mhz serial 4.5 - - ns normal read 9 - - ns tch(1) tclh clock high time 4pp 14 - - ns serial 4.5 - - ns normal read 9 - - ns tcl(1) tcll clock low time 4pp 14 - - ns tclch(2) clock rise time (3) (peak to peak) 0.1 - - v/ns tchcl(2) clock fall time (3) (peak to peak) 0.1 - - v/ns tslch tcss cs# active setup time (relative to sclk) 3 - - ns tchsl cs# not active hold time (relative to sclk) 3 - - ns tdvch tdsu data in setup time 2 - - ns tchdx tdh data in hold time 2 - - ns tchsh cs# active hold time (relative to sclk) 3 - - ns tshch cs# not active setup time (relative to sclk) 3 - - ns read 15 - - ns tshsl(3) tcsh cs# deselect time write/erase/program 50 - - ns 2.7v-3.6v - - 9 ns tshqz(2) tdis output disable time 3.0v-3.6v - - 9 ns loading: 30pf - - 9 ns tclqv tv clock low to output valid loading: 30pf/15pf loading: 15pf - - 8 ns tclqx tho output hold time 0 - - ns twhsl write protect setup time 20 - - ns tshwl write protect hold time 100 - - ns tdp(2) cs# high to deep power-down mode - - 10 us tres1(2) cs# high to standby mode without electronic signature read - - 20 us tres2(2) cs# high to standby mode with electronic signature read - - 20 us tw write status register cycle time - 40 100 ms tbp byte-program - 9 300 us tpp page program cycle time - 0.7 3 ms tse sector erase cycle time - 60 300 ms tbe block erase cycle time - 0.4 2.2 s tce chip erase cycle time - 3 15 s note1: tch + tcl must be greater than or equal to 1/f (fc or fr or f4pp). note2: value guaranteed by characterization, not 100% tested in production. note3: only applicable as a constraint for a wrsr instruction when srwd is set at 1. note4: test condition is shown as figure 4, 5.
gpr25l0805e ? generalplus technology inc. proprietary & confidential 24 nov 02, 2012 version: 1.0 10.5. timing analysis figure 6. serial input timing figure 7. output timing
gpr25l0805e ? generalplus technology inc. proprietary & confidential 25 nov 02, 2012 version: 1.0 figure 8. wp# setup timing and hold timing during wrsr when srwd=1 figure 9. write enable (wren) sequence (command 06) figure 10. write disable (wrdi) sequence (command 04)
gpr25l0805e ? generalplus technology inc. proprietary & confidential 26 nov 02, 2012 version: 1.0 figure 11. read identification (rdid) sequence (command 9f) figure 12. read status register (rdsr) sequence (command 05) figure 13. write status register (wrsr) sequence (command 01) figure 14. read data bytes (read) sequence (command 03)
gpr25l0805e ? generalplus technology inc. proprietary & confidential 27 nov 02, 2012 version: 1.0 figure 15. read at higher speed (fast_read) sequence (command 0b) figure 16. 2 x i/o read mode sequence (command bb) note: 1. si/sio0 or so/sio1 should be kept "00" or "11" in the first 2 dummy cycles. in other words, p2=p0 or p3=p1 is necessary.
gpr25l0805e ? generalplus technology inc. proprietary & confidential 28 nov 02, 2012 version: 1.0 figure 17. 4 x i/o read mode sequence (command eb) note: 1. hi-impedance is inhibited for the two clock cycles. 2. p7 p3, p6 p2, p5 p1 & p4 p0 (toggling) will enter the performance enhance mode.
gpr25l0805e ? generalplus technology inc. proprietary & confidential 29 nov 02, 2012 version: 1.0 figure 18. 4 x i/o read enhance performance mode sequence (command eb)
gpr25l0805e ? generalplus technology inc. proprietary & confidential 30 nov 02, 2012 version: 1.0 figure 19. sector erase (se) sequence (command 20) note: se command is 20(hex). figure 20. block erase (be) sequence (command d8) note: be command is d8(hex). figure 21. chip erase (ce) sequence (command 60 or c7) note: ce command is 60(hex) or c7(hex).
gpr25l0805e ? generalplus technology inc. proprietary & confidential 31 nov 02, 2012 version: 1.0 figure 22. page program (pp) sequence (command 02) figure 23. 4 x i/o page program (4pp) sequence (command 38) figure 24. deep power-down (dp) sequence (command b9)
gpr25l0805e ? generalplus technology inc. proprietary & confidential 32 nov 02, 2012 version: 1.0 figure 25. read electronic signature (res) sequence (command ab) figure 26. release from deep power-down (rdp) sequence (command ab)
gpr25l0805e ? generalplus technology inc. proprietary & confidential 33 nov 02, 2012 version: 1.0 figure 27. read electroni c manufacturer & device id (rems) sequence (command 90 or ef or df) notes: (1) add=00h will output the manufacturer's id fi rst and add=01h will output device id first (2) instruction is either 90(hex) or ef(hex) or df(hex). figure 28. power-up timing note: vcc (max.) is 3.6v and vcc (min.) is 2.7v.
gpr25l0805e ? generalplus technology inc. proprietary & confidential 34 nov 02, 2012 version: 1.0 table 11. power-up timing symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low 300 - us note: 1. the parameter is characterized only. 10.6. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh ). the status register conta ins 00h (all status register bits are 0).
gpr25l0805e ? generalplus technology inc. proprietary & confidential 35 nov 02, 2012 version: 1.0 11. recommended operating conditions 11.1. at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power-up. (ex: vcc a nd cs# ramp up simultaneously) if the timing in the figure is ignored, the device may not operate correctly. figure a. ac timing at device power-up symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v note1: sampled, not 100% tested. note2: for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the figure, please refer to "table 10. ac charact eristics".
gpr25l0805e ? generalplus technology inc. proprietary & confidential 36 nov 02, 2012 version: 1.0 12. erase and programming performance parameter min. typ. (1) max. (2) unit write status register cycle time(4) - 40 100 ms sector erase time - 60 300 ms block erase time - 0.4 2.2 s chip erase time - 3 15 s byte program time (via page program command) - 9 300 us page program time - 0.7 3 ms erase/program cycle 100,000 - - cycles note: 1. typical program and erase time assumes the following conditions: 25c, 3.3v, and checker board pattern. 2. under worst conditio ns of 85c and 2.7v. 3. system-level overhead is the time required to execut e the first-bus-cycle sequence for the programming command. 4. erase/program cycles comply with jedec jesd-47e & a117a standard. 13. data retention parameter condition min. max. unit data retention 55 ? c 20 - years
gpr25l0805e ? generalplus technology inc. proprietary & confidential 37 nov 02, 2012 version: 1.0 14. latch-up characteristics parameter min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vcc max input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test c onditions: vcc = 3.0v, one pin at a time.
gpr25l0805e ? generalplus technology inc. proprietary & confidential 38 nov 02, 2012 version: 1.0 15. ordering information product number package type gpr25l0805e ? hs13x package form - 8-sop rohs (green package) note1: code number is assigned for customer. note2: code number (n = a - z or 0 - 9, nn = 00 - 99); version (v = a - z). note3: package form number (x = 1 - 9, serial number).
gpr25l0805e ? generalplus technology inc. proprietary & confidential 39 nov 02, 2012 version: 1.0 16. package information 16.1. title: package outline for sop 8l (200mil) 16.2. dimensions (inch dimensions are derived from the original mm dimensions) symbol unit a a1 a2 b c d e e1 e l l1 s min. - 0.05 1.70 0.36 0.19 5.13 7.70 5.18 - 0.50 1.21 0.62 0 nom. - 0.15 1.80 0.41 0.20 5.23 7.90 5.28 1.27 0.65 1.31 0.74 5 mm max. 2.16 0.20 1.91 0.51 0.25 5.33 8.10 5.38 - 0.80 1.41 0.88 8 min. - 0.002 0.067 0.014 0.007 0.202 0.303 0.204 - 0.020 0.048 0.024 0 nom. - 0.006 0.071 0.016 0.008 0.206 0.311 0.208 0.050 0.026 0.052 0.029 5 inch max. 0.085 0.008 0.075 0.020 0.010 0.210 0.319 0.212 - 0.031 0.056 0.035 8 reference dwg. no. revision jedec eiaj issue date 6110-1401 3 - - -
gpr25l0805e ? generalplus technology inc. proprietary & confidential 40 nov 02, 2012 version: 1.0 17. disclaimer the information appearing in this public ation is believed to be accurate. integrated circuits sold by generalplus technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. generalplus makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of t he described chip(s) from patent infringem ent. furthermore, generalplus makes no warranty of merchantability or fitness for any purpose. generalplus reserves the right to halt production or alter the specifications and prices at any time without notice. acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing or ders. products described herein are intended for use in normal co mmercial applications. applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by generalplus for such applications. please note th at application circuits illustrated in this document are for reference purposes only.
gpr25l0805e ? generalplus technology inc. proprietary & confidential 41 nov 02, 2012 version: 1.0 18. revision history date revision# description page nov 02, 2012 1.0 original 41

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